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HY5DU561622FTP-5I / HY5DU561622FTP-4I
256M(16Mx16) DDR SDRAM
HY5DU561622F(L)TP-5I HY5DU561622F(L)TP-4I
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev. 1.1 / Mar. 2008 1
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Revision History
Revision No. 1.0 1.1 First Version Release Correction - P.3 Ordering Information History Draft Date Nov. 2007 Mar. 2008 Remark
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DESCRIPTION
The Hynix HY5DU561622FTP-5I, -4I series are a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth. The Hynix 16Mx16 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.
FEATURES
* * * * * * * * VDD, VDDQ = 2.5V + / - 0.2V for 200MHz VDD, VDDQ = 2.6V + 0.1 / -0.2V for 250MHz All inputs and outputs are compatible with SSTL_2 interface JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe (DQS) x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ) Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe * * * * * * * All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock Write mask byte controls by LDM and UDM Programmable /CAS latency 3 / 4 supported Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode Internal 4 bank operations with single pulsed /RAS tRAS Lock-Out function supported Auto refresh and self refresh supported 8192 refresh cycles / 64ms Full, Half and Matched Impedance(Weak) strength driver option controlled by EMRS Operation temperature : -40oC to 85oC
* * *
*
ORDERING INFORMATION
Part No. HY5DU561622FTP-4I HY5DU561622FTP-5I Power Supply (VDD, VDDQ) 2.6V + 0.1 / - 0.2V 2.5V + / - 0.2V Clock Frequency 250MHz 200MHz Max Data Rate 500Mbps/pin 400Mbps/pin interface SSTL-2 Temp IT Part Package 400mil 66pin TSOP-II
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PIN CONFIGURATION
V DD DQ0 VDDQ DQ1 DQ2 V SSQ DQ3 DQ4 V DDQ DQ5 DQ6 V SSQ DQ7 NC V DDQ LDQS NC V DD NC LDM /WE / CAS / RAS / CS NC BA0 BA1 A10/AP A0 A1 A2 A3 V DD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33
TOP VIEW
400 mil X 875mil 66 Pin TSOP - II 0.65mm Pin Pitch
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34
V SS DQ15 V SSQ DQ14 DQ13 V DDQ DQ12 DQ11 V SSQ DQ10 DQ9 V DDQ DQ8 NC V SSQ UDQS NC V REF V SS UDM / CLK CLK CKE NC A12 A11 A9 A8 A7 A6 A5 A4 V SS
ROW and COLUMN ADDRESS TABLE
Items
Organization Row Address Column Address Bank Address Auto Precharge Flag Refresh
16Mx16
4M x 16 x 4banks A0 ~ A12 A0 ~ A8 BA0, BA1 A10 8K
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PIN DESCRIPTION
PIN CK, /CK TYPE Input DESCRIPTION Clock: CK and /CK are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of /CK. Output (read) data is referenced to the crossings of CK and /CK (both directions of crossing). Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit, and for output disable. CKE must be maintained high throughout READ and WRITE accesses. Input buffers, excluding CK, /CK and CKE are disabled during POWER DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after Vdd is applied. Chip Select : Enables or disables all inputs except CK, /CK, CKE, DQS and DM. All commands are masked when CS is registered high. CS provides for external bank selection on systems with multiple banks. CS is considered part of the command code. Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, Read, Write or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 is sampled during a precharge command to determine whether the PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected by BA0, BA1. The address inputs also provide the op code during a MODE REGISTER SET command. BA0 and BA1 define which mode register is loaded during the MODE REGISTER SET command (MRS or EMRS). Command Inputs: /RAS, /CAS and /WE (along with /CS) define the command being entered. Input Data Mask: DM(LDM,UDM) is an input mask signal for write data. Input data is masked when DM is sampled HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. LDM corresponds to the data on DQ0-Q7; UDM corresponds to the data on DQ8-Q15. Data Strobe: Output with read data, input with write data. Edge aligned with read data, centered in write data. Used to capture write data. LDQS corresponds to the data on DQ0-Q7; UDQS corresponds to the data on DQ8-Q15. Data input / output pin : Data Bus Power supply for internal circuits and input buffers. Power supply for output buffers for noise immunity. Reference voltage for inputs for SSTL interface. No connection.
CKE
Input
/CS
Input
BA0, BA1
Input
A0 ~ A12
Input
/RAS, /CAS, /WE
Input
LDM, UDM
Input
LDQS, UDQS DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ VREF NC
I/O I/O Supply Supply Supply NC
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FUNCTIONAL BLOCK DIAGRAM
4Banks x 4Mbit x 16 I/O Double Data Rate Synchronous DRAM
W rite Data Register 2-bit Prefetch Unit
32
16
In p u t B u ffer
DS
CLK /CLK CKE /CS /RAS /CAS LDM UDM
Bank Control
4Mx16/Bank0
S en se A M P
4Mx16 /Bank1
64
2 -b it Prefe tch U n it
O u tpu t B u ffer
Command Decoder
32
4Mx16 /Bank2
4Mx16 /Bank3
Mode Register
Row Decoder
DQ[0:15]
Column Decoder
A0-12
BA0,BA1
LDQS,UDQS
Address Buffer
Column Address Counter
CLK_DLL
Data Strobe Transmitter
DS Data Strobe Receiver
CLK, /CLK
DLL Block
Mode Register
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SIMPLIFIED COMMAND TRUTH TABLE
Command Extended Mode Register Set Mode Register Set Device Deselect No Operation Bank Active Read Read with Autoprecharge Write Write with Autoprecharge Precharge All Banks Precharge selected Bank Read Burst Stop Auto Refresh Entry Self Refresh Exit CKEn-1 H H H H H CKEn X X X X X CS L L H L L L RAS L L X H L H CAS L L X H H L WE L L X H H H CA RA L H L H H L X X
ADDR
A10/ AP OP code OP code X
BA
Note 1,2 1,2 1
V V
1 1 1,3 1 1,4 1,5 1 1 1 1
H
X
L
H
L
L
CA
V X V
H H H H L
X X H L H
L L L L H L H L H L H L
L H L L X H X H X H X V X
H H L L X H X H X H X V
L L H H X H X H X H X V
X
X
1 1
Entry Precharge Power Down Mode Exit
H
L
X
1 1 1 1
L
H
Active Power Down Mode
Entry Exit
H L
L H
X
1 1
( H=Logic High Level, L=Logic Low Level, X=Don't Care, V=Valid Data Input, OP Code=Operand Code, NOP=No Operation ) Note : 1. LDM/UDM states are Don't Care. Refer to below Write Mask Truth Table. 2. OP Code(Operand Code) consists of A0~A12 and BA0~BA1 used for Mode Register setting during Extended MRS or MRS. Before entering Mode Register Set mode, all banks must be in a precharge state and MRS command can be issued after tRP period from Prechagre command. 3. If a Read with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+tRP). 4. If a Write with Autoprecharge command is detected by memory component in CK(n), then there will be no command presented to activated bank until CK(n+BL/2+1+tDPL+tRP). Last Data-In to Prechage delay(tDPL) which is also called Write Recovery Time (tWR) is needed to guarantee that the last data has been completely written. 5. If A10/AP is High when Precharge command being issued, BA0/BA1 are ignored and all banks are selected to be precharged.
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WRITE MASK TRUTH TABLE
Function Data Write Data-In Mask Lower Byte Write / Upper Byte-In Mask Upper Byte Write / Lower Byte-In Mask CKEn-1 H H H H CKEn X X X X /CS, /RAS, /CAS, /WE X X X X LDM L H L H UDM L H H L
ADDR
A10/ AP X X X X
BA
Note
1,2 1,2 1,2 1,2
Note : 1. Write Mask command masks burst write data with reference to LDQS/UDQS(Data Strobes) and it is not related with read data. 2. LDM and UDM control lower byte(DQ0~7) and Upper byte(DQ8~15) respectively.
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OPERATION COMMAND TRUTH TABLE - I
Current State /CS H L L L IDLE L L L L L H L L L ROW ACTIVE L L L L L H L L L READ L L L L L H L WRITE L L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H L Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP Action NOP or power down3 NOP or power down3 ILLEGAL4 ILLEGAL4 ILLEGAL4 Row Activation NOP Auto Refresh or Self Refresh5 Mode Register Set NOP NOP ILLEGAL4 Begin read : optional AP6 Begin write : optional AP6 ILLEGAL4 Precharge7 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end Terminate burst Term burst, new read:optional AP8 ILLEGAL ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL4 Term burst, new read:optional AP8 Term burst, new write:optional AP
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OPERATION COMMAND TRUTH TABLE - II
Current State /CS L WRITE L L L H L L READ WITH AUTOPRECHARGE L L L L L L H L L WRITE AUTOPRECHARGE L L L L L L H L L L PRECHARGE L L L L L /RAS L L L L X H H H H L L L L X H H H H L L L L X H H H H L L L L /CAS H H L L X H H L L H H L L X H H L L H H L L X H H L L H H L L /WE H L H L X H L H L H L H L X H L H L H L H L X H L H L H L H L Address BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL4 Term burst, precharge ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 Continue burst to end Continue burst to end ILLEGAL ILLEGAL10 ILLEGAL10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP-Enter IDLE after tRP NOP-Enter IDLE after tRP ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,10 NOP-Enter IDLE after tRP ILLEGAL11 ILLEGAL11
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OPERATION COMMAND TRUTH TABLE - III
Current State /CS H L L L ROW ACTIVATING L L L L L H L L L WRITE RECOVERING L L L L L H L L WRITE RECOVERING WITH AUTOPRECHARGE L L L L L L H L REFRESHING L L /RAS X H H H H L L L L X H H H H L L L L X H H H H L L L L X H H H /CAS X H H L L H H L L X H H L L H H L L X H H L L H H L L X H H L /WE X H L H L H L H L X H L H L H L H L X H L H L H L H L X H L H Address X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP Command DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP Action NOP - Enter ROW ACT after tRCD NOP - Enter ROW ACT after tRCD ILLEGAL4 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,9,10 ILLEGAL4,10 ILLEGAL11 ILLEGAL11 NOP - Enter ROW ACT after tWR NOP - Enter ROW ACT after tWR ILLEGAL4 ILLEGAL ILLEGAL ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter precharge after tDPL NOP - Enter precharge after tDPL ILLEGAL4 ILLEGAL4,8,10 ILLEGAL4,10 ILLEGAL4,10 ILLEGAL4,11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tRC NOP - Enter IDLE after tRC ILLEGAL11 ILLEGAL11
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OPERATION COMMAND TRUTH TABLE - IV
Current State /CS L L WRITE L L L H L L L MODE REGISTER ACCESSING L L L L L /RAS H L L L L X H H H H L L L L /CAS L H H L L X H H L L H H L L /WE L H L H L X H L H L H L H L Address BA, CA, AP BA, RA BA, AP X OPCODE X X X BA, CA, AP BA, CA, AP BA, RA BA, AP X OPCODE Command WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS DSEL NOP BST READ/READAP WRITE/WRITEAP ACT PRE/PALL AREF/SREF MRS Action ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 NOP - Enter IDLE after tMRD NOP - Enter IDLE after tMRD ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11 ILLEGAL11
Note : 1. H - Logic High Level, L - Logic Low Level, X - Don't Care, V - Valid Data Input, BA - Bank Address, AP - AutoPrecharge Address, CA - Column Address, RA - Row Address, NOP - NO Operation. 2. All entries assume that CKE was active(high level) during the preceding clock cycle. 3. If both banks are idle and CKE is inactive(low level), then in power down mode. 4. Illegal to bank in specified state. Function may be legal in the bank indicated by Bank Address(BA) depending on the state of that bank. 5. If both banks are idle and CKE is inactive(low level), then self refresh mode. 6. Illegal if tRCD is not met. 7. Illegal if tRAS is not met. 8. Must satisfy bus contention, bus turn around, and/or write recovery requirements. 9. Illegal if tRRD is not met. 10. Illegal for single bank, but legal for other banks in multi-bank devices. 11. Illegal for all banks.
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CKE FUNCTION TRUTH TABLE
Current State CKEn-1 H L SELF REFRESH1 L L L L L H L POWER DOWN2 L L L L L H H H ALL BANKS IDLE4 H H H H H L ANY STATE OTHER THAN ABOVE H H L L CKEn X H H H H H L X H H H H H L H L L L L L L L L H L H L /CS X H L L L L X X H L L L L X X L H L L L L L X X X X X /RAS X X H H H L X X X H H H L X X L X H H H L L X X X X X /CAS X X H H L X X X X H H L X X X L X H H L H L X X X X X /WE X X H L X X X X X H L X X X X H X H L X X L X X X X X /ADD X X X X X X X X X X X X X X X X X X X X X X X X X X X Action INVALID Exit self refresh, enter idle after tSREX Exit self refresh, enter idle after tSREX ILLEGAL ILLEGAL ILLEGAL NOP, continue self refresh INVALID Exit power down, enter idle Exit power down, enter idle ILLEGAL ILLEGAL ILLEGAL NOP, continue power down mode See operation command truth table Enter self refresh Exit power down Exit power down ILLEGAL ILLEGAL ILLEGAL ILLEGAL NOP See operation command truth table ILLEGAL5 INVALID INVALID
Note : When CKE=L, all DQ and DQS must be in Hi-Z state. 1. CKE and /CS must be kept high for a minimum of 200 stable input clocks before issuing any command. 2. All command can be stored after 2 clocks from low to high transition of CKE. 3. Illegal if CK is suspended or stopped during the power down mode. 4. Self refresh can be entered only from the all banks idle state. 5. Disabling CK may cause malfunction of any bank which is in active state.
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SIMPLIFIED STATE DIAGRAM
MODE R E G IS T E R SET
MRS
ID L E
SREF SREX
SELF REFRESH
PDEN PDEX
POW ER DOW N
POW ER DOW N
AREF ACT
AUTO REFRESH
PDEN
BST
BANK A C T IV E
PDEX
READ W R IT E READAP
W R IT E
READ
P R E (P A LL)
W R IT E W IT H AUTOPRECHARGE
READ READAP W IT H AUTO PRECHARGE W R IT E A P
READ
W R IT E A P
W R IT E P R E (P A LL) P R E (P A LL)
PRECHARGE
P O W E R -U P
C o m m a n d In p u t A u t o m a t ic S e q u e n c e
P O W E R A P P L IE D
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POWER-UP SEQUENCE AND DEVICE INITIALIZATION
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Except for CKE, inputs are not recognized as valid until after VREF is applied. CKE is an SSTL_2 input, but will detect an LVCMOS LOW level after VDD is applied. Maintaining an LVCMOS LOW level on CKE during power-up is required to guarantee that the DQ and DQS outputs will be in the High-Z state, where they will remain until driven in normal operation (by a read access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM requires a 200us delay prior to applying an executable command. Once the 200us delay has been satisfied, a DESELECT or NOP command should be applied, and CKE should be brought HIGH. Following the NOP command, a PRECHARGE ALL command should be applied. Next a EXTENDED MODE REGISTER SET command should be issued for the Extended Mode Register, to enable the DLL, then a MODE REGISTER SET command should be issued for the Mode Register, to reset the DLL, and to program the operating parameters. After the DLL reset, tXSRD(DLL locking time) should be satisfied for read command. After the Mode Register set command, a PRECHARGE ALL command should be applied, placing the device in the all banks idle state. Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a MODE REGISTER SET command for the Mode Register, with the reset DLL bit deactivated low (i.e. to program operating parameters without resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation. 1. Apply power - VDD, VDDQ, VTT, VREF in the following power up sequencing and attempt to maintain CKE at LVCMOS low state. (All the other input pins may be undefined.
No power sequencing is specified during power up or power down given the following cirteria : * VDD and VDDQ are driven from a single power converter output. * VTT is limited to 1.44V (reflecting VDDQ(max)/2 + 50mV VREF variation + 40mV VTT variation). * VREF tracks VDDQ/2. * A minimum resistance of 42 ohms (22 ohm series resistor + 22 ohm parallel resistor - 5% tolerance) limits the input current from the VTT supply into any pin. If the above criteria cannot be met by the system design, then the following sequencing and voltage relationship must be adhered to during power up : Voltage description VDDQ VTT VREF 2. 3. 4. 5. 6. Sequencing After or with VDD After or with VDDQ After or with VDDQ Voltage relationship to avoid latch-up < VDD + 0.3V < VDDQ + 0.3V < VDDQ + 0.3V
Start clock and maintain stable clock for a minimum of 200usec. After stable power and clock, apply NOP condition and take CKE high. Issue Extended Mode Register Set (EMRS) to enable DLL. Issue Mode Register Set (MRS) to reset DLL and set device to idle state with bit A8=high. (An additional 200 cycles(tXSRD) of clock are required for locking DLL) Issue Precharge commands for all banks of the device.
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7. 8.
Issue 2 or more Auto Refresh commands. Issue a Mode Register Set command to initialize the mode register with bit A8 = Low.
Power-Up Sequence
VDD
VDDQ
tVTD
VTT VREF
/CLK CLK
tIS tIH
CKE
LVCMOS Low Level
CMD
NOP
PRE
EMRS
MRS
NOP
PRE
AREF
MRS
ACT
RD
DM
ADDR
CODE
CODE
CODE
CODE
CODE
A10
CODE
CODE
CODE
CODE
CODE
BA0, BA1
CODE
CODE
CODE
CODE
CODE
DQS
DQ'S
T=200usec tRP
tMRD
tMRD
tRP
tRFC tXSRD*
tMRD
Power UP VDD and CK stable
Precharge All
EMRS Set
MRS Set Reset DLL (with A8=H)
Precharge All
2 or more Auto Refresh
MRS Set (with A8=L)
Non-Read Command
READ
* 200 cycle(tXSRD) of CK are required (for DLL locking) before Read Command
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MODE REGISTER SET (MRS)
The mode register is used to store the various operating modes such as /CAS latency, addressing mode, burst length, burst type, test mode, DLL reset. The mode register is program via MRS command. This command is issued by the low signals of /RAS, /CAS, /CS, /WE and BA0. This command can be issued only when all banks are in idle state and CKE must be high at least one cycle before the Mode Register Set Command can be issued. Two cycles are required to write the data in mode register. During the the MRS cycle, any command cannot be issued. Once mode register field is determined, the information will be held until resetted by another MRS command.
BA1 0
BA0 0
A12
A11
A10
A9
A8 DR
A7 TM
A6
A5
A4
A3 BT
A2
A1
A0
RFU
CAS Latency
Burst Length
BA0 0 1
MRS Type MRS EMRS
A7 0 1
Test Mode Normal Test Burst Length
A8 0 1
DLL Reset No Yes
A2
A1
A0 Sequential Interleave Reserved 2 4 8 Reserved Reserved Reserved Reserved
0 0 0 0
0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1
Reserved 2 4 8 Reserved Reserved Reserved Reserved
A6 0 0 0 0 1 1 1 1
A5 0 0 1 1 0 0 1 1
A4 0 1 0 1 0 1 0 1
CAS Latency Reserved Reserved Reserved 3 4 Reserved Reserved Reserved A3 0 1
1 1 1 1
Burst Type Sequential Interleave
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BURST DEFINITION
Burst Length 2 Starting Address (A2,A1,A0) XX0 XX1 X00 4 X01 X10 X11 000 001 010 8 011 100 101 110 111 Sequential 0, 1 1, 0 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3, 4, 5, 6, 7 1, 2, 3, 4, 5, 6, 7, 0 2, 3, 4, 5, 6, 7, 0, 1 3, 4, 5, 6, 7, 0, 1, 2 4, 5, 6, 7, 0, 1, 2, 3 5, 6, 7, 0, 1, 2, 3, 4 6, 7, 0, 1, 2, 3, 4, 5 7, 0, 1, 2, 3, 4, 5, 6 Interleave 0, 1 1, 0 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 0, 1, 2, 3, 4, 5, 6, 7 1, 0, 3, 2, 5, 4, 7, 6 2, 3, 0, 1, 6, 7, 4, 5 3, 2, 1, 0, 7, 6, 5, 4 4, 5, 6, 7, 0, 1, 2, 3 5, 4, 7, 6, 1, 0, 3, 2 6, 7, 4, 5, 2, 3, 0, 1 7, 6, 5, 4, 3, 2, 1, 0
BURST LENGTH & TYPE
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The burst length determines the maximum number of column locations that can be accessed for a given Read or Write command. Burst lengths of 2, 4 or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a Read or Write command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst wraps within the block if a boundary is reached. The block is uniquely selected by A1-Ai when the burst length is set to two, by A2-Ai when the burst length is set to four and by A3-Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both Read and Write bursts. Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Burst Definitionon Table
CAS LATENCY
The Read latency or CAS latency is the delay in clock cycles between the registration of a Read command and the
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availability of the first burst of output data. The latency can be programmed 3 or 4 or 5 clocks. If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with clock edge n + m. Reserved states should not be used as unknown operation or incompatibility with future versions may result.
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The HY5DU561622FTP supports Full, Half strength driver and Matched impedance driver, intended for lighter load and/ or point-to-point environments. The Full drive strength for all output is specified to be SSTL_2, CLASS II. Half strength driver is to define about 50% of Full drive strength and Matched impedance driver, about 30% of Full drive strength.
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EXTENDED MODE REGISTER SET (EMRS)
The Extended Mode Register controls functions beyond those controlled by the Mode Register; these additional functions include DLL enable/disable, output driver strength selection(optional). These functions are controlled via the bits shown below. The Extended Mode Register is programmed via the Mode Register Set command ( BA0=1 and BA1=0) and will retain the stored information until it is programmed again or the device loses power. The Extended Mode Register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements will result in unspecified operation.
BA1 0 BA0 1 A12 A11 A10 A9 A8 A7 A6 DS A5 A4 A3 A2 A1 DS A0 DLL
RFU*
RFU*
BA0 0 1
MRS Type MRS EMRS
A0 0 1
DLL enable Enable Diable
A6 0 0 1 1
A1 0 1 0 1
Output Driver Impedance Control Full Half RFU* RFU*
* All bits in RFU address fields must be programmed to Zero, all other states are reserved for future usage.
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ABSOLUTE MAXIMUM RATINGS
Parameter
Ambient Temperature Storage Temperature Voltage on Any Pin relative to VSS Voltage on VDD relative to VSS Voltage on VDDQ relative to VSS Output Short Circuit Current Power Dissipation Soldering Temperature Time
Symbol
TA TSTG VIN, VOUT VDD VDDQ IOS PD TSOLDER
Rating
-40 ~ 85 -55 ~ 125 -0.5 ~ 3.6 -0.5 ~ 3.6 -0.5 ~ 3.6 50 1 260 10
o
Unit
o o
C C
V V V mA W C sec
Note : Operation at above absolute maximum rating can adversely affect device reliability
DC OPERATING CONDITIONS
Parameter
Power Supply Voltage Power Supply Voltage Input High Voltage Input Low Voltage Termination Voltage Reference Voltage
(TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Symbol
VDD VDDQ VIH VIL VTT VREF
Min
2.4 2.4 VREF + 0.15 -0.3 VREF - 0.04 0.49*VDDQ
Typ.
2.6 2.6 VREF 0.5*VDDQ
Max
2.7 2.7 VDDQ + 0.3 VREF - 0.15 VREF + 0.04 0.51*VDDQ
Unit
V V V V V V
Note
5 5, 1 2 3
Note : 1. VDDQ must not exceed the level of VDD. 2. VIL (min) is acceptable -1.5V AC pulse width with 5ns of duration. 3. VIH (max) is acceptable VDDQ + 1.5V AC pulse width with < 5ns of duration 4. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of the same. Peak to peak noise on VREF may not exceed 2% of the dc value. 5. Supports 250/ 200 Mhz
DC CHARACTERISTICS I
Parameter
Input Leakage Current Output Leakage Current Output High Voltage Output Low Voltage
(TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Symbol
ILI ILO VOH VOL
Min.
-5 -5 VTT + 0.76 -
Max
5 5 VTT - 0.76
Unit
uA uA V V
Note
1 2 IOH = -15.2mA IOL = +15.2mA
Note : 1. VIN = 0 to 3.6V, All other pins are not tested under VIN = 0V. 2. DOUT is disabled, VOUT = 0 to 2.7V
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DC CHARACTERISTICS II
(TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Parameter
Symbol
Test Condition
One bank; Active - Read - Precharge; Burst Length=4; tRC=tRC(min); tCK=tCK(min); address and control inputs changing once per clock cycle; IOUT=0mA All banks idle; Power down mode; CKE=Low, tCK=tCK(min) /CS=High, All banks idle; tCK=tCK(min); CKE=High; address and control inputs changing once per clock cycle. VIN=VREF for DQ, DQS and DM One bank active; Power down mode ; CKE=Low, tCK=tCK(min) /CS=HIGH; CKE=HIGH; One bank; ActivePrecharge; tRC=tRAS(max); tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle Burst=2;Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); IOUT=0mA Burst=2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK=tCK(min); DQ, DM and DQS inputs changing twice per clock cycle tRC=tRFC(min); All banks active CKE=<0.2V; External clock on; tCK=tCK(min)
Speed 4 5
Unit Note
Operating Current
IDD1
160
150
mA
Precharge Power Down Standby Current
IDD2P
20
20
mA
Idle Standby Current
IDD2N
80
70
mA
Active Power Down Standby Current
IDD3P
55
50
mA
Active Standby Current
IDD3N
90
80
mA
IDD4R Operating Current
IDD4W
220
200
mA
220
200
mA
Auto Refresh Current Self Refresh Current
IDD5 IDD6
200 5
180 5
mA
mA
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AC OPERATING CONDITIONS (TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Parameter Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.35 VREF - 0.35 VDDQ + 0.6 0.5*VDDQ+0.2 Max Unit V V V V 1 2 Note
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
AC OPERATING TEST CONDITIONS (TA=-40 ~ 85oC, Voltage referenced to VSS = 0V)
Parameter Reference Voltage Termination Voltage AC Input High Level Voltage (VIH, min) AC Input Low Level Voltage (VIL, max) Input Timing Measurement Reference Level Voltage Output Timing Measurement Reference Level Voltage Input Signal maximum peak swing Input minimum Signal Slew Rate Termination Resistor (RT) Series Resistor (RS) Output Load Capacitance for Access Time Measurement (CL) Value VDDQ x 0.5 VDDQ x 0.5 VREF + 0.35 VREF - 0.35 VREF VTT 1.5 1 50 25 30 Unit V V V V V V V V/ns pF
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AC CHARACTERISTICS - I (AC operating conditions unless otherwise noted)
Parameter Row Cycle Time (Manual Precharge) Row Cycle Time (Auto Precharge) Auto Refresh Row Cycle Time Row Active Time Row Address to Column Address Delay Row Active to Row Active Delay Column Address to Column Address Delay Row Precharge Time Last Data-In to Precharge Delay (Write Recovery Time : tWR) Last Data-In to Read Command Auto Precharge Write Recovery + Time System Clock Cycle Time Clock High Level Width Clock Low Level Width Data-Out edge to Clock edge Skew DQS-Out edge to Clock edge Skew DQS-Out edge to Data-Out edge Skew Data-Out hold time from DQS Clock Half Period Data Hold Skew Factor Input Setup Time Input Hold Time Write DQS High Level Width Write DQS Low Level Width Clock to First Rising edge of DQS-In Data-In Setup Time to DQS-In (DQ & DM) Precharge CL = 4.0 CL = 3.0 Symbol 4 Min 15 17 18 40 5 2 2 1 5 4 2 9 4.0 0.45 0.45 -0.7 -0.7 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.85 0.4 Max 70K 7.0 0.55 0.55 0.7 0.7 0.4 0.4 0.6 0.6 1.15 Min 12 14 14 40 4 2 2 1 4 3 2 7 5.0 0.45 0.45 -0.7 -0.7 tHPmin -tQHS tCH/L min 0.75 0.75 0.4 0.4 0.75 0.4 5
Unit Note
Max 70K 7.0 0.55 0.55 0.7 0.7 0.45 0.5 0.6 0.6 1.25 CK CK CK ns CK CK CK CK CK CK CK CK ns ns CK CK ns ns ns ns ns ns ns ns CK CK CK ns 3 1, 6 1, 5 6 2 2
tRC tRC_APCG tRFC tRAS tRCDRD tRCDWT tRRD tCCD tRP tDPL tDRL tDAL
tCK tCH tCL tAC tDQSCK tDQSQ tQH tHP tQHS tIS tIH tDQSH tDQSL tDQSS tDS
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4 Min 0.4 0.9 0.4 0 1.5 0.4 2 200
1tCK + tIS 2tCK + tIS
Parameter Data-In Hold Time to DQS-In (DQ & DM) Read DQS Preamble Time Read DQS Postamble Time Write DQS Preamble Setup Time Write DQS Preamble Hold Time Write DQS Postamble Time Mode Register Set Delay Exit Self Refresh to Any Execute Command Except Read Command Read Command Average Periodic Refresh Interval Note : tDH
Symbol
5
Unit Note
Max 1.1 0.6 0.6 7.8
Min 0.4 0.9 0.4 0 1.5 0.4 2 200
1tCK + tIS 2tCK + tIS
Max 1.1 0.6 0.6 7.8 ns CK CK ns ns CK CK CK CK CK us 4 3
tRPRE tRPST tWPRES tWPREH tWPST tMRD tXSC tPDEX tPDEX_RD tREFI
Power Down Exit Time
-
-
1. This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter. 2. Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE. 3. Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM. 4. Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM. 5. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH). 6. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of tDQSQmax, the pulse width distortion of on-chip clock circuits, data pin to pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers. 7. DQS, DM and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transitions through the DC region must be monotonic.
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AC CHARACTERISTICS - II
Frequency 250MHz (4.0ns) 200MHz (5.0ns) CL 4 3 tRC
(Manual Precharge)
tRC_APCG
(AUTO Precharge)
tRFC 18 14
tRAS 40ns 40ns
tRCDRD 5 4
tRCDWT 2 2
tRP 5 4
tDAL 9 7
Unit tCK tCK
15 12
17 14
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CAPACITANCE (TA=25oC, f=1MHz )
Parameter Input Clock Capacitance Input Capacitance Input / Output Capacitanc CK, CK All other input-only pins DQ, DQS, DM Pin Symbol CCK CIN CIO Min 2.0 2.0 4.0 Max 3.0 3.0 5.0 Unit pF pF pF
Note : 1. VDD = min. to max., VDDQ = 2.3V to 2.7V, VODC = VDDQ/2, VOpeak-to-peak = 0.2V 2. Pins not under test are tied to GND. 3. These values are guaranteed by design and are tested on a sample basis only.
OUTPUT LOAD CIRCUIT
VTT
RT=50
Output
Zo=50
VREF
CL=30pF
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PACKAGE INFORMATION
400mil 66pin Thin Small Outline Package
Unit : mm(Inch)
11.94 (0.470) 11.79 (0.462)
10.26 (0.404) 10.05 (0.396)
BASE PLANE
22.33 (0.879) 22.12 (0.871)
0 ~ 5 Deg.
0.65 (0.0256) BSC
0.35 (0.0138) 0.25 (0.0098)
SEATING PLANE
1.194 (0.0470) 0.991 (0.0390)
0.15 (0.0059) 0.05 (0.0020)
0.597 (0.0235) 0.406 (0.0160)
0.210 (0.0083) 0.120 (0.0047)
Note : Package do not mold protrusion. Allowable protrusion of both sides is 0.4mm.
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